MOSFET structure and method of fabricating the same

ABSTRACT

A MOSFET structure and a method of forming it are described. The thickness of a portion of the gate dielectric layer of the MOSFET structure adjacent to the drain region is increased to form a bird&#39;s beak structure. The gate-to-drain overlap capacitance is reduced by the bird&#39;s beak structure.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates generally to an integrated circuit. Moreparticularly, the present invention relates to a structure of ametal-oxide-semiconductor field effect transistor (MOSFET) and afabrication method thereof.

2. Description of Related Art

For high-frequency applications of the MOSFET, e.g. radio frequency (RF)communication and high-speed analog and digital integrated circuits,effects of the internal parasitic capacitances of the MOSFET must betaken into account. Internal parasitic capacitances of the MOSFETinclude the gate-to-drain overlap capacitance, which arises because thedrain region extends slightly under the gate electrode.

The effects of the internal capacitances are analyzed herein withreference to FIGS. 1A-1D. FIG. 1A illustrates the MOSFET common-sourceamplifier configuration. Three large-valued capacitors C1, C2, and C3are used to couple the gate G, source S and drain D of a MOSFET Q tosignal source Vi in s-domain, ground 100 and load resistance R_(L),respectively. This amplifier has an output voltage Vo in s-domain. Thesignal generator generating the signal source Vi has a resistance Rs. Adc current source I is used to bias the MOSFET Q, and is connected to anegative supply voltage −Vss. A large resistor R_(G) connects the gate Gto ground 100, and a resistor R_(D) connects the drain D to a positivesupply voltage V_(DD). It's assumed that the source S of the MOSFET Q isconnected to the substrate, and in the following analysis of thehigh-frequency response of the MOSFET common-source amplifier of FIG. 1Athese capacitors C1, C2, and C3 act as perfect short circuits.

FIG. 1B illustrates a small-signal equivalent circuit of the MOSFETcommon-source amplifier of FIG. 1A. In FIG. 1B, a small-signalequivalent circuit model for the MOSFET is used to replace the MOSFET Qof FIG. 1A. The small-signal equivalent circuit model includes thegate-to-source parasitic capacitance Cgs with a voltage Vgs across itstwo terminals, gate-to-drain parasitic capacitance Cgd, a dependentcurrent source g_(m)Vgs, and an output resistance r_(o), in which theMOSFET Q has a transconductance g_(m). The parasitic capacitance betweenthe drain D and source S (or substrate) is usually neglected in anapproximate analysis.

In most situations of interest, the MOSFET operates in the saturationregion. When the MOSFET Q is in the saturation region, the parasiticcapacitance Cgs includes the gate-to-channel capacitance, thegate-to-source overlap capacitance and the gate-to-substrate parasiticcapacitance. The gate-to-channel capacitance is the major component ofthe parasitic capacitance Cgs. The parasitic capacitance Cgd is entirelyan overlap capacitance between the drain D and the gate G, and has atypical value of 1 to 10 fF (femto-Farad). As shown in FIG. 1B, theoutput resistance r_(o), resistor R_(D) and load resistance R_(L) arecombined to be an equivalent resistance R′_(L).

FIG. 1C illustrates a simplified version of the small-signal equivalentcircuit of FIG. 1B. A Thevenin voltage ViR_(G)/(R_(S)+R_(G)) and aThevenin resistance R′(equal to R_(S) in parallel with R_(G)) areobtained by applying Thevenin's theorem at the input side of the circuitof FIG. 1B. Since the overlap capacitance Cgd is small, the currentthrough it is very small and thus can be neglected in determining theoutput voltage Vo. Therefore, the output voltage Vo can be expressed asVo≈g _(m) VgsR′ _(L)

FIG. 1D illustrates the input (gate) side circuit of FIG. 1C afterreplacing the overlap capacitance Cgd with the equivalent Millercapacitance C_(M) at the input side between the gate G and ground 100.Using the ratio of the voltages at the two sides of the overlapcapacitance Cgd of FIG. 1CVo/Vgs=−g _(m) R′ _(L)enables us to find the equivalent Miller capacitanceC _(M) =Cgd(1+g _(m) R′ _(L))

With reference to FIG. 1D, the parasitic capacitance Cgs and theequivalent Miller capacitance C_(M) are in parallel, so they can becombined to be an equivalent capacitance C_(T). The input side circuitin FIG. 1D, an input RC circuit, is a circuit of a first-order low-passfilter whose time constant is C_(T)R′. This first-order circuitdetermines the high-frequency response of the common-source amplifier ofFIG. 1A, introducing a dominant high-frequency pole. The dominanthigh-frequency pole represents the upper 3-dB frequency ω_(H) which isω_(H)=1/C _(T) R′Thus the high-frequency gain A_(H) of the common-source amplifier can beexpressed asA _(H) =A _(M)(1/[1+s/ω _(H)])where s is the complex frequency, and A_(H) is the midband gain. Thehigh-frequency response analysis described above can be found and isexplained in more detail in “Microelectronic Circuits”, InternationalThomson Publishing, 3 ed, chapter 7, by Adel S. Sedra and Kenneth C.Smith.

According to the above analysis, the overlap capacitance Cgd plays animportant role in determining the high-frequency response. The overlapcapacitance Cgd affects the equivalent capacitance C_(T), therebyaffecting the upper 3-dB frequency ω_(H) and the high-frequency voltagegain A_(H). This is the Miller effect. If the overlap capacitance Cgd isreduced, the upper 3-dB frequency ω_(H) and the high-frequency gainA_(H) can be increased. On the other hand, since the parasiticcapacitance Cgs is an important factor affecting the MOSFET deviceparameters, including the threshold voltage Vt and the drain-to-sourcecurrent I_(DS), and thus affecting device performance, thegate-to-source overlap capacitance shouldn't be reduced.

Accordingly, there is a need for a MOSFET fabricating method that can beused to reduce the gate-to-drain overlap capacitance Cgd, and thus toimprove the high-frequency response of MOSFET amplifiers.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a method offabricating a MOSFET device for reducing the gate-to-drain overlapcapacitance, thus improving the high-frequency response of MOSFETamplifiers.

Another objective of the present invention is to provide a MOSFETstructure for reducing the gate-to-drain overlap capacitance, thusimproving the high-frequency response of MOSFET amplifiers.

According to an embodiment of the present invention, a method offabricating a MOSFET device includes the following steps. First, a gatestructure is formed on a substrate. The gate structure comprises a gatedielectric layer and a conductive layer. A masking layer is then formedto cover the gate structure and the substrate. Next, the masking layeris etched to expose a side of the gate structure and a region of asurface of the substrate adjacent to the side. Next, an oxidationprocess is performed on part of the exposed side of the gate structure,such that a bottom corner of the exposed gate structure is oxidized toform a bird's beak structure. The masking layer is then removed.Finally, a source region and a drain region are formed in the substraterespectively adjacent to two sides of the gate structure. The drainregion is adjacent to the bird's beak structure and the exposed side.

According to another embodiment of the present invention, a method offabricating a MOSFET device includes the following steps. First, a gatestructure is formed on a substrate. The gate structure comprises a gatedielectric layer and a conductive layer. A masking layer is then formedto cover the gate structure and the substrate. Next, implant ions aredirected onto the masking layer at an angle so as to shield part of themasking layer against the ions. Next, the masking layer is selectivelyetched so as to expose a side of the gate structure and a region of asurface of the substrate adjacent to the side. An oxidation process isthen performed on part of the exposed side of the gate structure, suchthat a bottom corner of the exposed gate structure is oxidized to form abird's beak structure. The masking layer is then removed. Finally, asource region and a drain region are formed in the substraterespectively adjacent to two sides of the gate structure. The drainregion is adjacent to the bird's beak structure and the exposed side.

According to an objective of the present invention, a MOSFET structureis described as follows. A gate dielectric layer is located on asubstrate, and a gate is located on the gate dielectric layer. There area source region and a drain region in the substrate, adjacent to thegate, respectively. A portion of the gate dielectric layer adjacent tothe drain region has a bird's beak structure, so as to reduce thegate-to-drain overlap capacitance between the gate and the drain region.

Advantages of the present invention include the following. Since aportion of the gate dielectric layer adjacent to the drain region is abird's beak structure, the gate-to-drain overlap capacitance is reduced.Because a bird's beak structure is not present at the overlap portionbetween the gate and the source region, after forming the bird's beakstructure adjacent to the drain region, the threshold voltage and thedrain-to-source current are not significantly affected. In conclusion,after the gate-to-drain overlap capacitance is reduced by the presenceof the bird's beak structure, no significant change occurs in the dc andlow-frequency operation performance of the MOSFET, whereas thehigh-frequency operation performance of the MOSFET is much improved.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the presentinvention will become better understood with regard to the followingdescription, appended claims, and accompanying drawings where:

FIG. 1A illustrates the MOSFET common-source amplifier configuration;

FIG. 1B illustrates a small-signal equivalent circuit of the MOSFETcommon-source amplifier of FIG. 1A;

FIG. 1C illustrates a simplified version of the small-signal equivalentcircuit of FIG. 1B;

FIG. 1D illustrates the input side circuit of FIG. 1C after replacingthe overlap capacitance Cgd with the equivalent Miller capacitance C_(M)at the input side between the gate G and ground 100;

FIG. 2 illustrates a cross section of a MOSFET structure according to anembodiment of the invention;

FIG. 3 is an enlarged illustration of the bird's beak structure 220 a ofFIG. 2;

FIGS. 4A-4E illustrate cross sections of a fabrication process of aMOSFET structure according to a preferred embodiment of the invention;and

FIGS. 5A-5F illustrate cross sections of a fabrication process of aMOSFET structure according to another preferred embodiment of theinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

References will now be made to the preferred embodiments of the presentinvention. Wherever possible, the same reference numbers are used in thedrawings and the description to refer to the same or substantiallysimilar elements.

FIG. 2 illustrates a cross section of a MOSFET structure according to anembodiment of the invention. A gate dielectric layer 220 and a gate 210are located on a substrate 200. There are a source region 230 and adrain region 240 in the substrate 200, both of which are adjacent to andpartially extend under the gate 210. A portion of the gate dielectriclayer 220 adjacent to the drain region 240 has a bird's beak structure220 a with increased thickness, so as to reduce the gate-to-drainoverlap capacitance between the gate 210 and the drain region 240.

Analytic Calculation of the Overlap Capacitance Value

The following device characteristics, dimensions and values are assumedfor the purpose of the analytic calculation of the gate-to-drain overlapcapacitance. The MOSFET structure in FIG. 2 is an N-channel MOSFET. Thematerial of the gate dielectric layer 220 is for instance silicondioxide and the thickness thereof is 40 angstroms. The channel length ofthis N-channel MOSFET is 0.2 micrometers (μm). When the bird's beakstructure 220 a with increased thickness is not present, and thisportion is the same as the portion of the gate dielectric layer 220 onthe other side of the gate 210 adjacent to the source region 230, theoverlap capacitance between the gate 210 and the drain region 240 is1.328 fF. When the bird's beak structure 220 a with increased thicknessis present, the calculation of the overlap capacitance between the gate210 and the drain region 240 is as follows.

FIG. 3 is an enlarged illustration of the bird's beak structure 220 a ofFIG. 2. Referring to FIG. 3, the thickness D_(O) of the gate dielectriclayer 220 except the bird's beak structure 220 a is equal to 40angstroms. The angle θ between the oblique side of the bird's beakstructure 220 a and the horizontal is 30°. The channel width W (notshown) of this N-channel MOSFET is equal to 10 micrometers, and thelength L of the bird's beak structure 220 a along the direction of thechannel is equal to 0.06 micrometers. The starting point of the obliqueside of the bird's beak structure 220 a is regarded as the origin of arectangular coordinate system formed by an x-axis and a y-axis. Anypoint on the oblique side of the bird's beak structure 220 a has aheight y, which is equal to the slope r of the oblique side times the xvalue of the point. The slope r of the oblique side of the bird's beakstructure 220 a is expressed in equation (1).r=tan θ  (1)

According to the definition of a capacitor formed by two parallelconductive plates separated by a dielectric medium, the overlapcapacitance C between the gate 210 and the drain region 240 is equal tothe stored charge ΔQ in the dielectric medium divided by the electricpotential difference ΔV between the two parallel plates, and is alsoequal to the dielectric constant ε of the dielectric medium times thearea A of the two parallel plates, and further divided by the distance Dbetween the two parallel plates, as shown in equation (2).$\begin{matrix}{C = {\frac{\Delta\quad Q}{\Delta\quad V} = \frac{ɛ\quad A}{D}}} & (2)\end{matrix}$

Therefore, the formula for the overlap capacitance C between the gate210 and the drain region 240 is a definite integration of equation (2),as shown in equation (3). In this case, A is equal to Wdx, D is equal toD_(O)+rx, and x is from 0 to L. $\begin{matrix}\begin{matrix}{C = {ɛ\quad W{\int{\frac{1}{D_{0} + {rx}}{\mathbb{d}x}}}}} \\{= {ɛ\quad\frac{W}{r}{\int_{0}^{L}{\frac{1}{( {{D_{0}/r} + x} )}\quad{\mathbb{d}x}}}}} \\{= {{ɛ\quad\frac{W}{r}{\ln( {{D_{0}/r} + x} )}}❘_{0}^{L}}} \\{= {ɛ\quad\frac{W}{r}{\ln( \frac{D_{0} + {L*r}}{D_{0}} )}}}\end{matrix} & (3)\end{matrix}$

Using the numerical values of all variables and constants in equation(3), the value of the overlap capacitance C between the gate 210 and thedrain region 240 can be found to be about 0.348 fF. According to thecalculation and analysis, it can be seen that after forming the bird'sbeak structure 220 a, the overlap capacitance C between the gate 210 andthe drain region 240 is reduced by about 74% of the original value 1.328fF.

First Embodiment

FIGS. 4A-4E illustrate cross sections of a fabrication process of aMOSFET structure according to a preferred embodiment of the invention.With reference to FIG. 4A, a dielectric layer and a conductive layer arefirst sequentially formed on a P-type substrate 400. The material of thedielectric layer is, for example, oxide, and preferably is silicondioxide. The dielectric layer is formed by, for example, thermaloxidation. The material of the conductive layer is, for example,polysilicon, and the conductive layer is formed by, for example,chemical vapor deposition (CVD). A photolithography and etching processis then performed on the dielectric layer and the conductive layer todefine a gate 410 and a gate dielectric layer 420. The gate 410 is aportion of the conductive layer, and the gate dielectric layer 420 is aportion of the dielectric layer. The gate 410 and the gate dielectriclayer 420 can be collectively called a gate structure. Next, a maskinglayer 430 is formed to cover the gate structure and the substrate 400.The material of the masking layer 430 is, for example, nitride, andpreferably is silicon nitride. The masking layer 430 is formed by, forexample, CVD.

With reference to FIG. 4B, a photoresist layer 440 is then used topartially cover the masking layer 430, and the rest of the masking layer430 not covered by the photoresist layer 440 is etched to expose a sideof the gate structure and a region of a surface of the substrate 400adjacent to the side. If the material of the masking layer 430 issilicon nitride, a solution comprising phosphoric acid, for example, canbe used to selectively etch (remove) part of the masking layer 430. Withreference to FIG. 4C, the photoresist layer 440 is then removed, and anetching is performed using, for example, a solution comprisinghydrofluoric acid (HF) to laterally etch part of the gate dielectriclayer 420 on the exposed side, in order to expose a bottom corner 415 ofthe gate structure. The lateral etching is, for example, an isotropicetching.

With reference to FIG. 4D, an oxidation process is then performed onpart of the exposed side of the gate structure, such that the bottomcorner 415 of the gate structure is oxidized to form a bird's beakstructure 420 a. This oxidation process is, for example, a thermaloxidation. The oxide on the surface of the exposed substrate 400 and thegate 410 resulting from the oxidation process is then removed, thuscompleting the structure shown in FIG. 4D.

With reference to FIG. 4E, the masking layer 430 is then removed, and anN-type source region 450 and an N-type drain region 460 are formed inthe substrate 400, which are respectively adjacent to two sides of thegate structure. The source region 450 and the drain region 460 areformed by, for example, ion implantation, and the drain region 460 isadjacent to the bird's beak structure 420 a and the exposed side. TheN-channel MOSFET structure is now completed, as shown in FIG. 4E.

The function of the bird's beak structure 420 a is to reduce the overlapcapacitance between the gate 410 and the drain region 460. It should beunderstood that the step of laterally etching part of the gatedielectric layer 420 described above might alternatively be omitted.Performing this lateral etching can help control the shape of the bird'sbeak structure 420 a formed.

In this embodiment, the channel length of the N-channel MOSFET structureis 0.2 micrometers, and the thickness of the gate dielectric layer 420except the bird's beak structure 420 a is 40 angstroms. The originalunit length gate-to-drain overlap capacitance value before forming thebird's beak structure 420 a is 0.451 fF/μm, whereas after forming thebird's beak structure 420 a the unit length overlap capacitance valuebetween the gate 410 and the drain region 460 becomes 0.307 fF/μm.Therefore, the unit length overlap capacitance value is reduced by about32%. At the same time, the threshold voltage Vt and the drain-to-sourcecurrent I_(DS) do not shift much, and each still remains in a respectiverange of ideal values. The threshold voltage Vt shifts by about 20millivolts (mV). In addition, some other implantation processes can beperformed to help maintain ideal device characteristics.

Second Embodiment

FIGS. 5A-5F illustrate cross sections of a fabrication process of aMOSFET structure according to another preferred embodiment of theinvention. With reference to FIG. 5A, a dielectric layer and aconductive layer are first sequentially formed on a P-type substrate500. The material of the dielectric layer is, for example, oxide, andpreferably is silicon dioxide. The dielectric layer is formed by, forexample, thermal oxidation. The material of the conductive layer is, forexample, polysilicon, and the conductive layer is formed by, forexample, CVD. A photolithography and etching process is then performedon the dielectric layer and the conductive layer to define a gate 520and a gate dielectric layer 510. The gate 520 is a portion of theconductive layer, and the gate dielectric layer 510 is a portion of thedielectric layer. The gate 520 and the gate dielectric layer 510 can becollectively called a gate structure.

With reference to FIG. 5B, a masking layer 540 is then formed to coverthe gate structure and the substrate 500. The material of the maskinglayer 540 is, for example, oxide, and the masking layer 540 is formedby, for example, CVD. With reference to FIG. 5C, an ion implantation 550is then performed, in which implant ions are directed onto the maskinglayer 540 at an angle and the shadow effect of the gate 520 is utilized,so as to shield part of the masking layer 540 against the ions. The ionsource used in the ion implantation 550 is, for example, nitrogen, argonor other heavy ions.

With reference to FIG. 5D, a selective etching, e.g. a wet etching, isthen performed to remove part of the masking layer 540 with implantedions, so as to expose a side of the gate structure and a region of asurface of the substrate 500 adjacent to the side. If the material ofthe masking layer 540 is silicon dioxide, a solution comprisinghydrofluoric acid, for example, can be used to perform the selectiveetching, in which the etching rate of silicon dioxide containingimplanted ions is faster than that of silicon dioxide without implantedions. Upon completing the selective etching, a portion 540 a of themasking layer 540 without implanted ions remains. Next, an etching isperformed using, for example, a solution comprising hydrofluoric acid toetch laterally part of the gate dielectric layer 510 on the exposedside, in order to expose a bottom corner 515 of the gate structure. Thelateral etching is, for example, an isotropic etching.

With reference to FIG. 5E, an oxidation process is then performed onpart of the exposed side of the gate structure, such that the bottomcorner 515 of the gate structure is oxidized to form a bird's beakstructure 510 a. This oxidation process is, for example, a thermaloxidation. The remaining portion 540 a of the masking layer 540, and theoxide on the surface of the exposed part of the substrate 500 and thegate 520 resulting from the oxidation process are then removed, thuscompleting the structure shown in FIG. 5E.

With reference to FIG. 5F, an N-type source region 550 and an N-typedrain region 560 are then formed in the substrate 500, which arerespectively adjacent to two sides of the gate structure. The sourceregion 550 and the drain region 560 are formed by, for example, ionimplantation, and the drain region 560 is adjacent to the bird's beakstructure 510 a and the exposed side. The N-channel MOSFET structure isnow completed, as shown in FIG. 5F.

The function of the bird's beak structure 510 a is to reduce the overlapcapacitance between the gate 520 and the drain region 560. It should beunderstood that the step of laterally etching part of the gatedielectric layer 510 described above might alternatively be omitted.Performing this lateral etching can help control the shape of the bird'sbeak structure 510 a formed.

If the P-type substrates 400 and 500 in the two embodiments describedabove are replaced by N-type materials, and the source regions 450 and550 and the drain regions 460 and 560 are all P-type regions, aP-channel MOSFET structure can be made.

According to the preferred embodiments of the invention, advantages ofthe present invention include the following. Since a portion of the gatedielectric layer adjacent to the drain region is a bird's beakstructure, the gate-to-drain overlap capacitance is reduced. Because abird's beak structure is not present at the overlap portion between thegate and the source region, after forming the bird's beak structureadjacent to the drain region the threshold voltage Vt and thedrain-to-source current IDS are not significantly affected. Inconclusion, after the gate-to-drain overlap capacitance is reduced bythe presence of the bird's beak structure, no significant change occursin the dc and low-frequency operation performance of the MOSFET, whereasthe high-frequency operation performance of the MOSFET is much improved.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the present inventionwithout departing from the scope or spirit of the invention. In view ofthe foregoing, it is intended that the present invention covermodifications and variations of this invention provided they fall withinthe scope of the following claims and their equivalents.

1. A method of fabricating a MOSFET device, comprising: forming a gatestructure on a substrate, said gate structure comprising a gatedielectric layer and a conductive layer; forming a masking layer tocover said gate structure and the substrate; etching said masking layerto expose a side of said gate structure and a region of a surface of thesubstrate adjacent to the side; performing an oxidation process on partof the exposed side of said gate structure, such that a bottom corner ofthe exposed gate structure is oxidized to form a bird's beak structure;removing said masking layer; and forming a source region and a drainregion in the substrate respectively adjacent to two sides of said gatestructure, wherein said drain region is adjacent to said bird's beakstructure and the exposed side.
 2. The method of claim 1, wherein saidconductive layer comprises a polysilicon layer.
 3. The method of claim2, further comprising laterally etching part of said gate dielectriclayer on the exposed side before performing said oxidation process. 4.The method of claim 3, wherein the lateral etching step is performed byisotropic etching.
 5. The method of claim 1, wherein said gatedielectric layer comprises an oxide layer.
 6. The method of claim 1,wherein said masking layer comprises a nitride layer.
 7. The method ofclaim 1, wherein said masking layer comprises a silicon nitride layer.8. A method of fabricating a MOSFET device, comprising: forming a gatestructure on a substrate, said gate structure comprising a gatedielectric layer and a conductive layer; forming a masking layer tocover said gate structure and the substrate; directing implant ions ontosaid masking layer at an angle so as to shield part of said maskinglayer against the ions; selectively etching said masking layer so as toexpose a side of said gate structure and a region of a surface of thesubstrate adjacent to the side; performing an oxidation process on partof the exposed side of said gate structure, such that a bottom corner ofthe exposed gate structure is oxidized to form a bird's beak structure;removing said masking layer; and forming a source region and a drainregion in the substrate respectively adjacent to two sides of said gatestructure, wherein said drain region is adjacent to said bird's beakstructure and the exposed side.
 9. The method of claim 8, wherein saidconductive layer comprises a polysilicon layer.
 10. The method of claim8, wherein said gate dielectric layer comprises an oxide layer.
 11. Themethod of claim 8, wherein said masking layer comprises an oxide layer.12. The method of claim 11, wherein forming said masking layer isperformed by chemical vapor deposition.
 13. The method of claim 8,wherein the selective etching comprises a wet etching process.
 14. Themethod of claim 8, wherein said masking layer comprises a silicondioxide layer.
 15. The method of claim 14, wherein the selective etchingcomprises utilizing a solution comprising HF.
 16. The method of claim 8,wherein the projected ions comprise one of nitrogen ions and argon ions.17. The method of claim 8, further comprising laterally etching part ofsaid gate dielectric layer on the exposed side before performing saidoxidation process.
 18. The method of claim 17, wherein the lateraletching step is performed by isotropic etching.
 19. A MOSFET structure,comprising: a substrate; a gate dielectric layer on said substrate; agate on said gate dielectric layer; a source region in said substrate,said source region being adjacent to said gate; and a drain region insaid substrate, said drain region being adjacent to said gate, wherein aportion of said gate dielectric layer adjacent to said drain region hasa bird's beak structure, so as to reduce the gate-to-drain overlapcapacitance between said gate and said drain region.
 20. The structureof claim 19, wherein said gate comprises a polysilicon layer.
 21. Thestructure of claim 19, wherein said gate dielectric layer comprises anoxide layer.